TESTMESH – NplusT

NplusT is pleased to announce the public release of TEE.Sim.RRAM, a free simulation workspace for the TESTMESH platform that enables engineers and researchers to develop, validate, and explore Resistive RAM (RRAM) characterization flows without requiring physical hardware.

Designed for both newcomers and experienced users, TEE.Sim.RRAM provides an accessible environment for learning the TESTMESH ecosystem, prototyping measurement sequences, and evaluating test methodologies long before silicon or laboratory equipment become available.

With TEE.Sim.RRAM, NplusT continues its commitment to making advanced non-volatile memory characterization more accessible, enabling engineers to explore innovative test methodologies with lower entry barriers and faster development cycles.

What is TEE.Sim.RRAM?

TEE.Sim.RRAM is a ready-to-use workspace built on the TEE (TESTMESH Execution Engine) framework. It simulates a 32 × 32 (1024-cell) RRAM array using a physics-based software model that reproduces the key characteristics of real devices, including voltage-driven conductance switching, device-to-device parameter variation, and realistic measurement noise.

The simulator also preserves the state of every memory cell across sessions, allowing users to perform long-term characterization studies such as endurance and progressive degradation experiments.

Why it matters

Developing characterization software typically depends on access to specialized hardware, which is often limited during the early stages of a project. TEE.Sim.RRAM removes this dependency by providing a realistic virtual laboratory that runs on any Windows PC with TESTMESH and BarnieMAT installed.

This allows development teams to design and debug measurement algorithms, evaluate new characterization concepts, and train engineers in parallel with hardware development, significantly shortening the path from concept to experimental validation.

What’s included

TEE.Sim.RRAM is delivered with a comprehensive collection of ready-to-run Python examples covering the most common RRAM characterization procedures, including:

SET, RESET and READ operations
Endurance cycling
Incremental pulse programming experiments
Current-voltage (I-V) sweeps

Measurement results are stored in CSV format and can be imported directly into BarnieMAT for interactive visualization and advanced data analysis.

Get Started

TEE.Sim.RRAM is available today through the NplusT/TestMesh GitHub repository.

Installation requires the TESTMESH User Interface and BarnieMAT, both available from the NplusT partner portal. License keys are provided free of charge upon request by contacting info@n-plus-t.com.

NplusT has successfully delivered another TESTMESH TMA-100 characterization system to a leading semiconductor company developing advanced RRAM memristor technology, using it both for embedded storage and for analog in-memory computing (IMC) applications.
The delivery includes the first hardware and software extension based on the new TESTMESH Extension Unit architecture. The extension, named TXU-CROSSBAR, has been specifically developed to characterize analog vector-matrix multiplication (VMM) and, more generally, crossbar-structured arrays. TXU-CROSSBAR expands the capabilities of the TESTMESH platform while preserving full compatibility with the standard system, providing researchers with a flexible environment for evaluating increasingly complex emerging-memory architectures.
Analog IMC based on RRAM memristor arrays is one of the most promising approaches for accelerating artificial intelligence workloads with dramatically improved energy efficiency. At the same time, these devices introduce new characterization challenges, requiring highly flexible instrumentation capable of combining precise analog stimulus, synchronized measurements, programmable algorithms, and advanced software control. TXU-CROSSBAR has been designed specifically to address these requirements.

This delivery represents the third TESTMESH TMA-100 system supplied to the same customer. In parallel, NplusT has already received the purchase order for a fourth system, further confirming both the value of the TESTMESH platform and the confidence established through this long-term technical collaboration.
Beyond the equipment itself, this project reflects the close cooperation established between the engineering teams. Working together, they have translated challenging characterization requirements into a practical and scalable solution, demonstrating how a modular platform can evolve alongside the rapidly changing needs of emerging-memory research.
The TESTMESH Extension Unit represents an important milestone in the evolution of the TESTMESH family. It enables customer-specific capabilities to be integrated into a common platform without compromising maintainability or future evolution, allowing new application domains to be addressed while leveraging the same proven hardware and software infrastructure.
As research in emerging memories and analog computing continues to accelerate, NplusT remains committed to providing flexible characterization solutions that enable innovation and shorten the path from laboratory research to commercial products.
The repeat adoption of TESTMESH by the same customer demonstrates the scalability of the platform and the value of long-term engineering partnerships in bringing next-generation memory technologies from research to production.

Only a few days to go before the 18th IEEE International Memory Workshop takes place in Leuven, Belgium, from May 10 to 13, 2026.

NplusT will be there with its booth, ready to connect with innovators, researchers, and industry leaders shaping the future of memory technologies.
Discover our advanced testing and characterization solutions for NVM, specifically designed for emerging paradigms such as neuromorphic architectures, in-memory computing (IMC), and AI-driven systems.

Visit our booth and see how we enable precise, scalable, and high-performance testing for next-generation memory devices
Book a meeting with our experts and explore tailored solutions for your applications

NplusT is pleased to announce the receipt of a significant purchase order from IMEC, a world-leading research and innovation hub in nanoelectronics and digital technologies, for the supply of a TESTMESH TMA-100 platform together with a customized solution dedicated to the electrical characterization of advanced 3D NAND test chips.

The customized solution extends the flexibility of the TESTMESH TMA-100 platform, reinforcing its positioning as a scalable and modular test architecture for advanced semiconductor characterization. The system is being tailored to support complex device structures built on flash or emerging non-volatile technologies, while maintaining measurement integrity and optimized test time.

We are excited to announce the release of TME-101, a customized small-size non-volatile memory cycling system designed for the qualification of NVM macros.

TME-101 combines the capabilities of a single-device precision tester with parallel operation, enabling engineers to obtain solid statistical insight without compromising on signal quality.
A key strength of the system is its high-accuracy signal generation and precise measurement capability, supporting detailed characterization throughout the cycling process.

Another distinctive feature is the integrated temperature control, which eliminates the need for an external climatic chamber. The system provides:

Very fast and accurate temperature transitions
Independent temperature control on each socket

This approach allows reliability profiles to be built quickly, with controlled and repeatable conditions on every device.

TME-101 is the first in a series of upcoming configurations designed to address the growing need for accurate device management and deep data collection, which traditional chamber-based cyclers struggle to provide. At the same time, this architecture remains significantly more cost-effective than general-purpose parallel test systems.

More breakthroughs are coming.

Advanced characterization environment for PCM (Phase Change Memory) test arrays

Since 2011, NplusT has presented the MOCCA (MOst Creative Customer Award) annually to recognize and celebrate the user team that demonstrates outstanding creativity in applying NplusT products to innovative and impactful projects. The award reflects the shared commitment to exploration, collaboration, and technological advancement.
For 2025, the MOCCA Award has been granted to the STMicroelectronics, Global Technology R&D – PCM Excellence Center team, composed of Giulia Samanni (ePCM Process Architecture & Device Reliability Staff Engineer), Enrico Gomiero (ePCM Device Architecture & Design Principal Engineer) and Alessandro Motta (ePCM Characterization Staff Engineer), and managed by Roberto Annunziata, for the creation of an advanced characterization environment for PCM (Phase Change Memory) test arrays.
Through their innovative approach, the STMicroelectronics team has developed a solution, based on NplusT’s TESTMESH TMA-100 instrumentation platform, that greatly enhances the speed and efficiency of device characterization, opening new opportunities for deeper analysis and faster iteration in memory technology development. Their project exemplifies how close collaboration and creative application of NplusT tools can translate into tangible performance breakthroughs.
Tamas Kerekes, President and CEO of NplusT, commented:
“Working with the STMicroelectronics team was a perfect example of how shared technical curiosity and mutual trust can accelerate innovation. Their forward-thinking use of our NVM characterization tools to build a highly efficient PCM test environment not only demonstrates exceptional creativity but also sets a new benchmark for characterization speed. We are proud to see such a clear alignment between our vision and their execution.”
Roberto Annunziata, Global Technology R&D – PCM Excellence Center Director, STMicroelectronics:
“NplusT provided a perfect framework for an effective collaboration. Technical expertise of our partners and strong motivation to find solutions enabled working as a unique team, exploiting the wide field of competencies. Results jointly achieved are a value for the current projects and an example for future collaborations in different domains.”

The STMicroelectronics Global Technology R&D PCM Excellence Center team and NplusT's CTO Nicola Campanelli — The STMicroelectronics Global Technology R&D PCM Excellence Center team and NplusT’s CTO Nicola Campanelli

Visit us at booth #951, at the Future of Memory and Storage Summit, August 5^th-7^th at the Santa Clara Convention Center in Santa Clara, California .

We will be exhibiting TESTMESH, our non-volatile memory test system, and NanoCycler, a full-feature NAND characterization equipment. Stop by to discover more about our solutions, optimized to accelerate the bring-up of novel technologies for data storage and for neuromorphic in-memory computing.

Join us at the International Memory Workshop 2025 to discover our solutions designed for rapid and accurate characterization of emerging non-volatile memory technologies, facilitate faster time-to-market and enhanced engineering productivity.

📅 [May 18th-21st 2025] | 📍 [Monterey, CA, USA]
🔗 [IEEE IMW 2025]

Since 2011, NplusT has presented the MOCCA (MOst Creative Customer Award) annually to recognize and celebrate the user team that demonstrates exceptional creativity in applying NplusT products to innovative and impactful projects. This award highlights the spirit of collaboration and innovation that drives technological progress.

MOCCA 2024 has been assigned to the IHP team, lead by Christian Wenger, Department Head, and including Andrea Baroni and Eduardo Perez, Scientists of the Material Research team, as first users of the TESTMESH TMC-100 configuration.

Tamas Kerekes, President and CEO of NplusT, shared his thoughts:

“Engaging with the IHP team to understand their unique requirements, we identified the significant market potential for a new TESTMESH configuration tailored to the specific characterization needs of neuromorphic computational arrays, built on cutting-edge non-volatile memory technologies. Together, our engineering teams conceptualized a solution that not only meets these demands but also positions us to deliver a groundbreaking characterization tool for this rapidly evolving market. I deeply value the shared commitment to innovation and the collaborative effort to design architectures that align seamlessly with the ever-changing landscape of technological advancements.”

Christian Wenger, Department Head, Material Research in IHP:

“The TESTMESH TMC-100 equipment from NplusT provides us the opportunity to investigate HfO2 based RRAM arrays in the 1T-1R configuration for Vector-Matrix-Multiplication application. The tailored set-up enables the programming the RRAM devices using complex algorithms as well as the interference process by addressing lines of the array. We are looking forward to present the first electrical results soon and to strengthen the collaboration between NplusT and IHP.”

IHP’s Andrea Baroni And NplusT’s Alessandro Feriani with TMC-100

In the past, MOCCA was assigned to:

2011 Macronix
2012 STMicroelectronics
2013 IHP
2014 Infineon
2015 Tower
2016 STMicroelectronics
2017 Microsemi
2018 GAMAX
2019 Infineon
2020 LETI
2021 TENAFE
2022 STMicroelectronics
2023 WEEBIT

NplusT has achieved a major milestone with the granting of its second patent, further strengthening its intellectual property portfolio in cutting-edge testing solutions for electronic devices. This latest patent safeguards the company’s fast, multi-range, low-leakage current sensing circuitry, a critical technology for precise and efficient device evaluation, already applied in specific TESTMESH configurations.

Building on this momentum, NplusT is also advancing its third patent, currently pending approval. This innovation introduces a structured test system architecture, designed to interface seamlessly with electronic memory devices, optimizing the testing of matrix-arranged memory cells—particularly for emerging neuromorphic memory technologies. Such technology is the core of the TESTMESH TMC-100 equipment.

“These achievements reaffirm our commitment to technological excellence and continuous innovation.” said Tamas Kerekes, President and CEO of NplusT. “They further establish our company as a leading provider of non-volatile memory testing solutions, enabling the next generation of advanced memory devices.”

With a growing portfolio of proprietary technologies, NplusT continues to push the boundaries of non-volatile memory testing, delivering solutions that enhance speed, accuracy, and reliability in the rapidly evolving semiconductor landscape.

NplusT Releases TEE.Sim.RRAM: A Free Simulation Workspace for RRAM Test Flow Development

Enabling the Next Generation of Analog In-Memory Computing with TESTMESH

NplusT at IMW 2026

NplusT Receives Major Order from IMEC for TESTMESH TMA-100 and Customized 3D NAND Characterization Solution

TME-101 released

MOCCA 2025 awarded to STMicroelectronics

NplusT at FMS 2025

NplusT at IMW 2025

MOCCA 2024 awarded to IHP

NplusT Secures Second Patent, Advances Third Innovation

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