NplusT’s TESTMESH is the new engineering tester platform, based on a breakthrough architecture concept.
The members of the TESTMESH family represent high-performance, ready-to-start, all-in-one instruments for the development and engineering of novel non-volatile memory technologies.
Based on the technology development stage, TESTMESH offers several optimized configurations.

The hardware and software resources of the TESTMESH instruments support:

• Extremely fast algorithmic cycling
• Increased visibility on the cell and array status, characteristics and behavior
• Productivity of the technology and product engineers.

These features are obtained by:

• Algorithmic, 200MHz waveform generators with dynamic impedance control and with pulse selection in microseconds
• Fast current sensing circuits with setup time below microsecond and sampling speed in the dozens of nanosecond domain
• Current measurement range switch time in microseconds, essential to obtain write pulses and suitable read scales
• Threshold-programmable one-bit ADC to detect if the cell reached the desired state (sense amplifier emulation)
• Flexible, programmable hardware sequencer to reduce the interaction with the software
• Wafer and package level testing
• Graphical user interface with engineering and operator modes, editor for waveforms, cycles and flows
• Python and C++ programmability
• Seamless integration with BarnieMAT, array data analysis software