TESTMESH


TESTMESH

Millions of Cycles in a Flash


NplusT’s TESTMESH is the new engineering tester platform, based on a breakthrough architecture concept.
The members of the TESTMESH family represent high-performance, ready-to-start, all-in-one instruments for the development and engineering of novel non-volatile memory technologies.
Based on the technology development stage, TESTMESH offers several optimized configurations.

The hardware and software resources of the TESTMESH instruments support:

  • Extremely fast algorithmic cycling
  • Increased visibility on the cell and array status, characteristics and behavior
  • Productivity of the technology and product engineers.
TESTMESH TMA-100

TESTMESH family overview

These features are obtained by:

  • Algorithmic, 200MHz waveform generators with dynamic impedance control and with pulse selection in microseconds
  • Fast current sensing circuits with setup time below microsecond and sampling speed in the dozens of nanosecond domain
  • Current measurement range switch time in microseconds, essential to obtain write pulses and suitable read scales
  • Threshold-programmable one-bit ADC to detect if the cell reached the desired state (sense amplifier emulation)
  • Flexible, programmable hardware sequencer to reduce the interaction with the software
  • Wafer and package level testing
  • Graphical user interface with engineering and operator modes, editor for waveforms, cycles and flows
  • Python and C++ programmability
  • Seamless integration with BarnieMAT, array data analysis software

TESTMESH configurations

TESTMESH configurations



Customer testimonials

40-times faster test execution than on a high cost ATE

3-times higher engineering productivity related to another memory tester

Allows engineers to focus on “what-to-do” rather than “what-we-see”

TESTMESH Overview


Technologies

  • Flash (NAND, NOR, 3D)
  • ReRAM
  • PCM
  • FeRAM
  • MRAM
  • Memristor networks

Primary Functions:

  • Algorithmic and blind cycling
  • Characterization (IV, …) at programmable cycles
  • Topologic pattern generation
  • Various disturb operations (read, topologic. …)

Applications:

  • Technology evaluation
  • Reliability evaluation
  • Design validation
  • Characterization
  • Die sorting for engineering purposes
  • Failure analysis
  • Production monitor

TMA-100

For NVM cells and mini-arrays
  • For Every NVM Technology
    • For single cell devices and test arrays
    • On transistor- and resistor-based cells
    • Emulates charge pumps and sense amps
  • For Fastest Test Execution
    • Configurations in microseconds
    • Ultra-fast current sensing
    • Smart algorithms
  • For Highest Engineering Productivity
    • True Interactive Testing
    • Configurable test flows and algorithms in Python
    • Integrated prober control and data analysis

TMC-100

For evaluation of crossbar and computational arrays
  • For Crossbar and Analog Computing Arrays
    • Dedicated multiplexers and references
    • Emulated computational operations
    • High-accuracy drift detection
  • For Fast and Accurate Test Execution
    • Fast algorithmic cycling
    • Configuration in microseconds
    • Multi-bit storage emulation
  • For Highest Engineering Productivity
    • True Interactive Testing
    • Python and C++ customization
    • Integrated prober control and data analysis

TMY-100

For IP macros and final products
  • Optimized for Speed and Intelligence
    • Protocol-based algorithmic device management
    • Super-fast analog signal capture and bitmapping
    • On-the-fly response processing and decisions
  • Full-Feature Equipment
    • Minimal facility requirements
    • Structured integration of handlers and probers
    • Built-in support for expansions
  • Focus on Engineering Productivity
    • True Interactive Testing
    • Powerful development tools in Python and C++
    • Toolchain and data analysis integration

TMS-100

For NVM single cells
  • For Every Technology
    • For transistor and resistor-based cells
    • Emulates charge pumps and sense amps
    • Lightweight, minimal facility requirements
  • Speed-Optimized Architecture
    • Fast algorithmic cycling
    • Configuration in microseconds
    • Fast, accurate waveforms and current sensing
  • Focus on Engineering Productivity
    • True Interactive Testing
    • Configurable test flows in Python
    • Integrated prober control
  • Focus on Engineering Productivity
    • True Interactive Testing
    • Python and C++ programming
    • Integrated data analysis

Product Gallery

Resources

  • Articles
  • Videos
Articles

Reliability Testing of Emerging Non-Volatile MemoriesHow to Shorten Time-To-Result

Aug 2024

Read or download PDF

Maximizing Engineering Productivity with True Interactive Testing

Feb 2024

Read or download PDF

NVM Characterization in Each Technology Development Stage

Nov 2023

Read or download PDF

TESTMESH: Designed for Ultra-Fast Characterization of Non-Volatile Memories

Nov 2023

Read or download PDF

All-in-One Instrument for Complex Non-Volatile Memory Characterization Tasks

Oct 2023

Read or download PDF

Millions of Cycles in a Flash

May 2023

Read or download PDF

Videos
Jul 2023

TESTMESH TMA-100 – Millions of Cycles in a Flash

Product Overview

Watch video

Legal Office

Loc. Castelfranco 132
05026 Montecastrilli
Terni, Italy

+39 075 5714845

info@n-plus-t.com

Laboratories

Via Donatella 12
06132 San Martino in Campo
Perugia, Italy

Capitale Sociale (Paid-up Capital) € 121.000,00 I.V.
Cod. Fisc. / Partita IVA (Vat Number) 00702760554
Sede CCIAA / n. REA : TR / 69772, PG / 272888
Iscriz. Reg. Imprese TR n. 00702760554


Privacy