TESTMESH

Millions of Cycles in a Flash

NplusT’s TESTMESH is the new engineering tester platform, based on a breakthrough architecture concept.
The members of the TESTMESH family represent high-performance, ready-to-start, all-in-one instruments for the development and engineering of novel non-volatile memory technologies.
Based on the technology development stage, TESTMESH offers several optimized configurations.

The hardware and software resources of the TESTMESH instruments support:

Extremely fast algorithmic cycling
Increased visibility on the cell and array status, characteristics and behavior
Productivity of the technology and product engineers.

These features are obtained by:

Algorithmic, 200MHz waveform generators with dynamic impedance control and with pulse selection in microseconds
Fast current sensing circuits with setup time below microsecond and sampling speed in the dozens of nanosecond domain
Current measurement range switch time in microseconds, essential to obtain write pulses and suitable read scales
Threshold-programmable one-bit ADC to detect if the cell reached the desired state (sense amplifier emulation)
Flexible, programmable hardware sequencer to reduce the interaction with the software
Wafer and package level testing
Graphical user interface with engineering and operator modes, editor for waveforms, cycles and flows
Python and C++ programmability
Seamless integration with BarnieMAT, array data analysis software

TESTMESH configurations

40-times faster test execution than on a high cost ATE

3-times higher engineering productivity related to another memory tester

Allows engineers to focus on “what-to-do” rather than “what-we-see”

Flash (NAND, NOR, 3D)
ReRAM
PCM
FeRAM
MRAM
Memristor networks
…

Algorithmic and blind cycling
Characterization (IV, …) at programmable cycles
Topologic pattern generation
Various disturb operations (read, topologic. …)

Technology evaluation
Reliability evaluation
Design validation
Characterization
Die sorting for engineering purposes
Failure analysis
Production monitor

For Every NVM Technology
- For single cell devices and test arrays
- On transistor- and resistor-based cells
- Emulates charge pumps and sense amps
For Fastest Test Execution
- Configurations in microseconds
- Ultra-fast current sensing
- Smart algorithms

For Highest Engineering Productivity
- True Interactive Testing
- Configurable test flows and algorithms in Python
- Integrated prober control and data analysis

For Crossbar and Analog Computing Arrays
- Dedicated multiplexers and references
- Emulated computational operations
- High-accuracy drift detection
For Fast and Accurate Test Execution
- Fast algorithmic cycling
- Configuration in microseconds
- Multi-bit storage emulation

For Highest Engineering Productivity
- True Interactive Testing
- Python and C++ customization
- Integrated prober control and data analysis

Optimized for Speed and Intelligence
- Protocol-based algorithmic device management
- Super-fast analog signal capture and bitmapping
- On-the-fly response processing and decisions
Full-Feature Equipment
- Minimal facility requirements
- Structured integration of handlers and probers
- Built-in support for expansions

Focus on Engineering Productivity
- True Interactive Testing
- Powerful development tools in Python and C++
- Toolchain and data analysis integration

For Every Technology
- For transistor and resistor-based cells
- Emulates charge pumps and sense amps
- Lightweight, minimal facility requirements
Speed-Optimized Architecture
- Fast algorithmic cycling
- Configuration in microseconds
- Fast, accurate waveforms and current sensing
Focus on Engineering Productivity
- True Interactive Testing
- Configurable test flows in Python
- Integrated prober control