News – NplusT

NplusT has successfully completed the factory buy-off and shipped a customized TESTMESH TMA-100 system to imec, for the characterization and reliability evaluation of advanced 3D NAND test structures.

The solution is based on the TESTMESH TMA-100 platform combined with the TXU-NAND Extension Unit, developed to address the demanding electrical and connectivity requirements of complex 3D NAND test arrays.

Key capabilities:

32 bitlines and 32 wordlines, 8 banks with independently controlled top and bottom selectors, up to 8 source lines;
Measurement on both bitlines and source lines;
Fully analog stimulus and measurement, high-voltage operation up to 30 V, current sensing down to the nA range;
High-speed execution for endurance and reliability tests with very large numbers of program/erase/measure cycles, monitoring degradation continuously.

The modular TESTMESH architecture also allows the TXU-NAND Extension Unit to be positioned close to the probe station, minimizing critical signal paths and supporting signal integrity, while the main TMA-100 system can be located remotely.

Beyond the hardware, NplusT provides a library of NAND-specific test and characterization algorithms. Test flows and measurement sequences are fully programmable in Python and C++, providing researchers with the flexibility to implement and automate customized characterization methodologies. The system can also control automated probe stations, enabling complete wafer-level characterization and reliability test flows.

For this specific customer configuration, the complete equipment and software environment operates under Linux.

The shipment follows the purchase order announced earlier this year and marks the successful completion of the development, integration and factory acceptance phase of the project.

With the system now moving to imec, NplusT continues to expand the TESTMESH platform from emerging-memory characterization into advanced 3D NAND research, endurance testing and reliability evaluation.

TESTMESH TMA-100 and TXU NAND — TESTMESH TMA-100 and TXU-NAND

NplusT is pleased to announce the delivery of a NanoCycler to a customer in the United States. The equipment will be deployed to characterize NAND memory devices, configured to support the specific requirements of radiation testing and aerospace qualification.

The order underscores NanoCycler’s proven capability to deliver highly accurate, package-level characterization data—covering aging, endurance, retention, timing, and power profiling—under the demanding conditions required by mission-critical aerospace systems. Its fully independent per-package test architecture allows engineers to tailor test flows precisely to radiation and environmental test protocols, making it a natural fit for space and defense-grade qualification work.

Tamas Kerekes, President and CEO of NplusT, comments: “The project is another important milestone of our activities for the aerospace industry, started with a project launched in 2025 with ESA, PCB Design and Thales, and now reaching its final stage. This new delivery confirms the relevance of our technology for radiation testing and aerospace-grade qualification, and reflects the growing international recognition of NanoCycler as a reference NAND characterization platform.”

We are pleased to announce a new release of the NanoCycler library, delivering significant performance improvements for NAND BER (Bit Error Rate) collection and datalog generation.

Over time, we identified that one of the main performance limitations of the Python library was the time required to calculate NAND page bit errors and generate the associated datalog. This overhead could have a noticeable impact on total execution time, particularly for complex test flows.

With WS version 4.3.3, NanoCycler now includes native, integrated datalog support, substantially accelerating failure collection and reducing overall execution time by more than 3×.

For example, a complete TLC block of approximately 2,000 pages, tested across all Read Retry entries, now takes approximately:

20 seconds → 6 seconds

This optimization applies broadly to operations that require NAND BER extraction and generation of test log reports.

The result is faster test execution, more efficient failure analysis, and improved productivity for NAND characterization and reliability testing.

NplusT is pleased to announce the public release of TEE.Sim.RRAM, a free simulation workspace for the TESTMESH platform that enables engineers and researchers to develop, validate, and explore Resistive RAM (RRAM) characterization flows without requiring physical hardware.

Designed for both newcomers and experienced users, TEE.Sim.RRAM provides an accessible environment for learning the TESTMESH ecosystem, prototyping measurement sequences, and evaluating test methodologies long before silicon or laboratory equipment become available.

With TEE.Sim.RRAM, NplusT continues its commitment to making advanced non-volatile memory characterization more accessible, enabling engineers to explore innovative test methodologies with lower entry barriers and faster development cycles.

What is TEE.Sim.RRAM?

TEE.Sim.RRAM is a ready-to-use workspace built on the TEE (TESTMESH Execution Engine) framework. It simulates a 32 × 32 (1024-cell) RRAM array using a physics-based software model that reproduces the key characteristics of real devices, including voltage-driven conductance switching, device-to-device parameter variation, and realistic measurement noise.

The simulator also preserves the state of every memory cell across sessions, allowing users to perform long-term characterization studies such as endurance and progressive degradation experiments.

Why it matters

Developing characterization software typically depends on access to specialized hardware, which is often limited during the early stages of a project. TEE.Sim.RRAM removes this dependency by providing a realistic virtual laboratory that runs on any Windows PC with TESTMESH and BarnieMAT installed.

This allows development teams to design and debug measurement algorithms, evaluate new characterization concepts, and train engineers in parallel with hardware development, significantly shortening the path from concept to experimental validation.

What’s included

TEE.Sim.RRAM is delivered with a comprehensive collection of ready-to-run Python examples covering the most common RRAM characterization procedures, including:

SET, RESET and READ operations
Endurance cycling
Incremental pulse programming experiments
Current-voltage (I-V) sweeps

Measurement results are stored in CSV format and can be imported directly into BarnieMAT for interactive visualization and advanced data analysis.

Get Started

TEE.Sim.RRAM is available today through the NplusT/TestMesh GitHub repository.

Installation requires the TESTMESH User Interface and BarnieMAT, both available from the NplusT partner portal. License keys are provided free of charge upon request by contacting info@n-plus-t.com.

NplusT has received a new purchase order from a leading European semiconductor manufacturer for an additional TESTMESH TMA-100 characterization system dedicated to embedded non-volatile memory (NVM) technology development and reliability evaluation.

The new system will complement an existing TESTMESH installation already in operation at the customer’s R&D facilities. Following the successful deployment of the first platform, the customer decided to expand its characterization capacity in order to support the increasing demand for advanced memory development activities.

One of the key benefits reported by the customer has been the significant increase in characterization and reliability evaluation throughput. By combining fully synchronized analog and digital signal generations and measurements, fast current sensing circuits and engineering-oriented programmability, the TESTMESH platform enables engineers to complete complex experiments in a fraction of the time required by conventional laboratory setups. Faster execution translates directly into shorter development cycles and higher engineering productivity.

The newly ordered TMA-100 system will further increase available test capacity while maintaining full compatibility with the customer’s existing measurement environment, allowing test programs, methodologies and characterization flows to be shared seamlessly across multiple systems.

TESTMESH TMA-100 for advanced non-volatile memory technology development and reliability evaluation

TESTMESH has been specifically designed for research and development of emerging and embedded non-volatile memory technologies, providing a highly flexible platform capable of adapting to rapidly evolving device architectures and test methodologies. Its modular architecture allows researchers to configure the instrumentation required for a wide range of electrical characterization and reliability experiments without compromising measurement accuracy or execution speed.

This second order further confirms the value of programmable characterization platforms as semiconductor companies continue to accelerate the development of next-generation embedded memory technologies. This order represents another example of customers expanding existing TESTMESH installations as characterization workloads continue to grow.

NplusT has successfully delivered another TESTMESH TMA-100 characterization system to a leading semiconductor company developing advanced RRAM memristor technology, using it both for embedded storage and for analog in-memory computing (IMC) applications.
The delivery includes the first hardware and software extension based on the new TESTMESH Extension Unit architecture. The extension, named TXU-CROSSBAR, has been specifically developed to characterize analog vector-matrix multiplication (VMM) and, more generally, crossbar-structured arrays. TXU-CROSSBAR expands the capabilities of the TESTMESH platform while preserving full compatibility with the standard system, providing researchers with a flexible environment for evaluating increasingly complex emerging-memory architectures.
Analog IMC based on RRAM memristor arrays is one of the most promising approaches for accelerating artificial intelligence workloads with dramatically improved energy efficiency. At the same time, these devices introduce new characterization challenges, requiring highly flexible instrumentation capable of combining precise analog stimulus, synchronized measurements, programmable algorithms, and advanced software control. TXU-CROSSBAR has been designed specifically to address these requirements.

This delivery represents the third TESTMESH TMA-100 system supplied to the same customer. In parallel, NplusT has already received the purchase order for a fourth system, further confirming both the value of the TESTMESH platform and the confidence established through this long-term technical collaboration.
Beyond the equipment itself, this project reflects the close cooperation established between the engineering teams. Working together, they have translated challenging characterization requirements into a practical and scalable solution, demonstrating how a modular platform can evolve alongside the rapidly changing needs of emerging-memory research.
The TESTMESH Extension Unit represents an important milestone in the evolution of the TESTMESH family. It enables customer-specific capabilities to be integrated into a common platform without compromising maintainability or future evolution, allowing new application domains to be addressed while leveraging the same proven hardware and software infrastructure.
As research in emerging memories and analog computing continues to accelerate, NplusT remains committed to providing flexible characterization solutions that enable innovation and shorten the path from laboratory research to commercial products.
The repeat adoption of TESTMESH by the same customer demonstrates the scalability of the platform and the value of long-term engineering partnerships in bringing next-generation memory technologies from research to production.

Only a few days to go before the 18th IEEE International Memory Workshop takes place in Leuven, Belgium, from May 10 to 13, 2026.

NplusT will be there with its booth, ready to connect with innovators, researchers, and industry leaders shaping the future of memory technologies.
Discover our advanced testing and characterization solutions for NVM, specifically designed for emerging paradigms such as neuromorphic architectures, in-memory computing (IMC), and AI-driven systems.

Visit our booth and see how we enable precise, scalable, and high-performance testing for next-generation memory devices
Book a meeting with our experts and explore tailored solutions for your applications

NplusT is pleased to announce the receipt of a significant purchase order from IMEC, a world-leading research and innovation hub in nanoelectronics and digital technologies, for the supply of a TESTMESH TMA-100 platform together with a customized solution dedicated to the electrical characterization of advanced 3D NAND test chips.

The customized solution extends the flexibility of the TESTMESH TMA-100 platform, reinforcing its positioning as a scalable and modular test architecture for advanced semiconductor characterization. The system is being tailored to support complex device structures built on flash or emerging non-volatile technologies, while maintaining measurement integrity and optimized test time.

We are pleased to share an important milestone in our company’s journey.

Our team and activities have continued to grow, leading us to expand our office space. As of today, our headquarters has doubled its surface area, creating a larger and more functional environment to support current operations and upcoming developments.
This expansion is not only a physical change, but a reflection of our continuous growth and our commitment to innovation, collaboration, and long-term development. The new space will allow us to better accommodate our team, strengthen internal workflows, and support future projects as we continue to evolve.

We would like to thank our customers, partners, and collaborators for being part of this journey. We look forward to sharing the next steps with you as we continue to grow together.

We are excited to announce the release of TME-101, a customized small-size non-volatile memory cycling system designed for the qualification of NVM macros.

TME-101 combines the capabilities of a single-device precision tester with parallel operation, enabling engineers to obtain solid statistical insight without compromising on signal quality.
A key strength of the system is its high-accuracy signal generation and precise measurement capability, supporting detailed characterization throughout the cycling process.

Another distinctive feature is the integrated temperature control, which eliminates the need for an external climatic chamber. The system provides:

Very fast and accurate temperature transitions
Independent temperature control on each socket

This approach allows reliability profiles to be built quickly, with controlled and repeatable conditions on every device.

TME-101 is the first in a series of upcoming configurations designed to address the growing need for accurate device management and deep data collection, which traditional chamber-based cyclers struggle to provide. At the same time, this architecture remains significantly more cost-effective than general-purpose parallel test systems.

More breakthroughs are coming.

NplusT Ships Advanced 3D NAND Characterization System to imec

NplusT Delivers NanoCycler to U.S. Aerospace Customer

New NanoCycler Library Release Improves NAND Failure Collection Performance

NplusT Releases TEE.Sim.RRAM: A Free Simulation Workspace for RRAM Test Flow Development

Leading European IDM Expands TESTMESH Capacity for Embedded Non-Volatile Memory Development

Enabling the Next Generation of Analog In-Memory Computing with TESTMESH

NplusT at IMW 2026

NplusT Receives Major Order from IMEC for TESTMESH TMA-100 and Customized 3D NAND Characterization Solution

Our Office Is Growing: A New Space for Future Developments

TME-101 released

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