June 4, 2024

A leading European semiconductor manufacturer has chosen NplusT’s TESTMESH TMA-100 for the characterization of new emerging non-volatile technology devices. The decision was based on the significant speed advantage that TMA-100 offers, being several hundred times faster than competitive solutions.



May 6, 2024

NplusT – as gold sponsor of the event – will exhibit the TESTMESH non-volatile memory test system, aiming to accelerate the bring-up of novel technologies for data storage and in-memory neuromorphic computing.

Technology researchers and  product developers benefit from a compact, all-in-one instrument, embedding all resources necessary for the characterization. They can focus on the analysis rather than spending time and effort for the integration of a complex test bench. TESTMESH’s speed-optimized architecture and the engineering-oriented software accelerates their process to obtain reliable results.

Looking forward to meet you, see you in Seoul!



February 20, 2024

As a tradition spanning more than a decade, NplusT assigned the MOCCA award also in 2023, honoring the user of NplusT products and services demonstrating the highest creativity, imagination, and dedication.

This year, the award was granted to the team of Weebit Nano, a provider of ReRAM non-volatile memory (NVM) technology, for their introduction of the TESTMESH TMA-100 NVM characterization equipment in their workflow. The Weebit team includes: Ori Livne, Director of Testing; Alessandro Bricalli PhD, R&D Engineer; Giuseppe Piccolboni PhD, R&D Engineer; and Matan Guttman, Test Engineer.

Tamás Kerekes, President and CEO of NplusT:

I have been following Weebit Nano since their very early days and I was impressed by how quickly the team was able to bring up a very new, extremely challenging technology. I am happy to support the company on their path to success. Weebit Nano is among the first users of our latest non-volatile memory characterization equipment, TESTMESH TMA-100, and certainly the first to apply it across multiple stages of technology development, from basic test devices to complex modules with embedded micro and digital interface. I am looking forward to continuing being part of Weebit Nano’s technology evaluation process.

Ilan Sever, VP of R&D, of Weebit Nano:

When developing a new memory technology like Weebit ReRAM, selecting the best testing and characterization solutions is a priority. We are delighted to partner with the team at NplusT, making its TESTMESH TMA-100 a key part of our flow. Together we designed the software, load boards and probe cards, going deep into every technical aspect.
At Weebit Nano, our products often have distinct working methodologies, and the TMA-100 easily accommodates these different procedures. This includes for example the ability to easily collaborate on the same platform with our R&D partner CEA-Leti.
Across our developments, the TMA-100 has saved us a lot of time and effort through product flexibility, the ability to reuse past developments, and the close support we receive from NplusT.

Weebit’s Ori Livne (left) and Matan Guttman (right) with the TESTMESH TMA-100
Weebit’s Ori Livne (left) and Matan Guttman (right) with the TESTMESH TMA-100


January 27, 2023

NplusT was featured on the 68th issue of HiPEAC magazine with an article on the 2nd FTTE project POP-LEC, for the optimization of the power consumption of CPS/ IoT devices, developed in the SMART4ALL H2020 framework and currently in its advanced industrialization stage.

Tamás Kerekes, president and CEO of NplusT, explains how the the company teamed up with Hungarian design house PCB Design to build the equipment prototype.

The complete issue is available at this link.



March 7, 2021

Every year, NplusT assigns the MOCCA (MOst Creative Customer Award) to those users, whose innovative applications and solutions enhance the utilization and performance of NplusT products. The year 2020 MOCCA has been assigned to Niccolò Castellani, R&D Engineer at CEA-LETI, Grenoble, for developing a software platform for the automation of non-volatile memory test flow execution on NplusT’s test equipment.

Tamas Kerekes, President and CEO of NplusT:
“I am really happy to see the way how Niccolò and the LETI team approached their specific requirements. The software framework, which Niccolò has created on top of the execution environment of the tester, enables the easy development of characterization programs for a wide range of novel, emerging non-volatile memory technologies. We plan to continue supporting LETI, providing innovative test platforms which enable fast and accurate measurements, contributing to develop high-performance, low-power, reliable storage devices.”

Niccolo Castellani, R&D engineer at CEA-Leti:
“I started this project a couple of years ago, having already experienced test developing and data analysis for research and industrial requirements. I’ve been always convinced about the real need of versatility for the R&D of merging memories testing. Only NplusT was able to provide the right tools and the right support team to accomplish my objective: a hardware to user interface getting plug-and-play new designs and new algorithms in its environment. I’m willing to continue this great collaboration.”



October 2, 2020

Building on their successful memory testing technology, NplusT has extended this expertise to the design, validation and characterization of image sensor devices.

Physical View of Cell Currents

The array-organized analog cell structure of the image sensor is similar to non-volatile memory and lends itself to the reuse of the core NplusT memory testing technology that has been production-proven for decades.

 

Distribution of currents after post-processing

Specific needs of data analysis to support image sensors has resulted in additional innovation with the extension of BarnieMAT, NplusT’s popular array data analysis tool, adding an additional library containing processing functions dedicated to image sensors.



September 29, 2017

The NplusT engineering team, in cooperation with FPGArt, implemented and tested with success a new technology, pushing up the communication speed between the tester and the device under test. The experimental solution, applied for a next generation NVM device, reaches 1.6GT/sec data transfer rate. Mastering this new technology, the application range of the RIFLE test system extends and covers the latest mass storage components, stil maintaining the cost advantage and faster time-to-result related to competitive solutions.



May 24, 2016

The already rich set of functions of RIFLE-M has been extended by the possibility of measuring access times of memory arrays at high accuracy. This new function, implemented as a dedicated FPGA module, generates programmable signal skew with a 1 nsec resolution. The feature is supported by an application specific calibration software in order to compensate the overall system skew including test board. In the same time, shmoo functionality covers the access time as well.

One of the key customers of RIFLE-M declared that the availability of this new function allows the execution of the entire design validation flow on RIFLE-M so other test platforms can be “switched off”.


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