TESTMESH TMA-100


TESTMESH TMA-100

Millions of Cycles in a Flash


TMA-100 is the first member of NplusT’s TESTMESH, the new engineering tester platform, based on a breakthrough architecture concept.

TMA-100 represents a high-performance, cost-optimized, all-in-one instrument for the development and engineering of novel non-volatile memory technologies.

Evaluation and characterization of single cell devices and test arrays requires:

  • Accurate generation of analog waveforms
  • Extremely fast current sensing
  • Algorithmic execution of complex write/erase/set/reset procedures

The combination of these tasks and their fast execution is a crucial factor, in order to perform millions and even billions of cycles in a reasonable time: using traditional instrumentation it might take years! TMA-100 especially architected for this tasks can reduce those times by 3-4 orders of magnitude by:

  • Arbitrary and algorithmic, 200MHz waveform generators with dynamic impedance control and with pulse selection in microseconds
  • Fast current sensing circuits with setup time below microsecond and sampling speed in the dozens of nanosecond domain
  • Current measurement range switch time in microseconds, essential to obtain write pulses and suitable read scales
  • Threshold-programmable one-bit ADC to detect if the cell reached the desired state (sense amplifier emulation)
  • Flexible, programmable hardware sequencer to reduce the interaction with the software

TESTMESH TMA-100 Overview


The productivity of the test engineer is supported by:

  • Programmable switch matrix to route the TMA-100 resources to the terminals of the device under test
  • Low level API for extreme flexibility
  • Mid level API for easy programming in C++ and Python
  • Graphical user interface for waveform, cycle and flow definition
  • Seamless interface with BarnieMAT, the array data analysis software

Primary Functions:

  • Algorithmic and blind cycling
  • Characterization (IV) at programmable cycles
  • Topologic pattern generation
  • Various disturb operations (read, topologic)

Applications:

  • Non-volatile technology evaluation at single cell or at test array level
  • Evaluation of IP modules with digital interface still providing analog access to the cells
  • Process qualification
  • Process monitor
  • Wafer and package level testing

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