When people first think about testing NAND Flash, the obvious operations come to mind: program data, read it back, erase the block, and check whether the device works.

For NAND characterization and reliability engineering, however, this is only the beginning.

Modern 3D NAND—particularly TLC and QLC devices—requires engineers to understand how and why device behavior changes with cycling, temperature, read conditions, operating parameters and time. A simple pass/fail result cannot provide this information.

A recent technical demonstration performed together with our partner Saniffer provided a good opportunity to illustrate what device-level NAND characterization involves. Starting from a real NAND device, the demonstration explored several complementary measurements using the NplusT NanoCycler platform: cycling and BER analysis, threshold-voltage characterization, dynamic power measurement, command-sequence capture and temperature profiling.

Together, these measurements provide a much deeper picture of NAND behavior than conventional functional testing.

From Functional Testing to Device Characterization

At SSD level, much of the physical behavior of NAND is hidden behind the controller, firmware, ECC and Flash Translation Layer.

This is exactly what an SSD needs to do—but it also means that engineers investigating the NAND technology itself need to go underneath these abstraction layers.

Typical questions are very different from simply asking whether a device can successfully read or write:

• How does raw BER evolve with program/erase cycling?
• How much read margin remains at a particular read level?
• How does the threshold-voltage distribution change?
• Are some wordlines, pages or dies behaving differently from others?
• What happens to these characteristics with temperature?
• What are the actual current peaks during program and erase?
• Which command sequence was really executed when unexpected behavior occurred?

Answering these questions requires access to the NAND device at a much lower level.

Looking Inside the Read Window: Read Offset BER and Vth Analysis

One of the demonstrations combined Program/Erase cycling with Read Offset BER measurements.

Instead of reading the device only at its nominal read levels, NanoCycler can sweep the available read offsets and measure the corresponding raw bit error rate. This makes it possible to observe how the read margin changes around each threshold.

For TLC and especially QLC NAND, this becomes increasingly important. As more bits are stored in each cell, the available threshold-voltage windows become narrower and the margins between adjacent states become more critical.

The objective is therefore not simply to determine whether a page is readable. The engineer wants to understand where the read window is located, how wide it is and how it evolves.

The same experiment can be extended with Vth dump measurements. Memory contents acquired at multiple read levels and offsets can be processed to reconstruct the underlying threshold-voltage distributions.

This transforms a functional observation — “the BER increased” — into a physical characterization question:

What happened to the underlying Vth distributions to cause that increase?

That distinction is fundamental for technology development and reliability analysis. And it is crucial to understand where to set the read levels to minimize BER, helping the error correction engine to regenerate the original content.

Power Consumption: Average Current Does Not Tell the Whole Story

Another demonstration focused on the dynamic current consumed by the NAND device during different operations.

Datasheets typically provide current specifications for operating modes such as read, program and erase. For system design, however, the average value may not be sufficient.

Program and erase operations can produce short current peaks substantially higher than the average consumption. The behavior can also change when moving from single-plane to multi-plane operations.

NanoCycler can capture the current profile during NAND operations, allowing engineers to correlate current consumption with the actual activity of the device.

This information becomes important not only for NAND characterization, but also for SSD and embedded-system design. Power supplies, decoupling, thermal design and parallel-operation strategies must ultimately handle the dynamic behavior of the NAND device, not just its average consumption. Understanding power behavior, the supply subsystem will not crash without the need of over-dimensioning it.

Sequence Capture: What Did the NAND Actually See?

Characterizing new or unfamiliar NAND devices often means dealing with behavior that does not perfectly match expectations.

• Was the correct command sent?
• Was the address sequence correct?
• How long did the device remain busy?
• Was the feature configuration applied as intended?

NanoCycler’s Sequence Capture capability provides visibility into the actual interaction with the NAND device, including commands, addresses, data and device status.

This can be particularly valuable when developing support for new NAND generations or debugging early samples. An unexpected result does not necessarily mean that the NAND is defective—or that the test equipment is malfunctioning. The problem may originate from a command sequence, timing parameter, feature setting or status-handling method.

Capturing what actually happened provides a common factual basis for debugging and, when necessary, for discussion with the NAND manufacturer.

Temperature Is More Than a Set Point

Temperature strongly affects NAND behavior, including retention, Vth drift, BER and disturb mechanisms.

But even temperature itself deserves closer examination.

During the demonstration, different temperature set points were applied while both system temperature and the internal temperatures reported by different NAND dies were monitored.

The results showed an important practical reality: different dies inside the same package do not necessarily operate at exactly the same temperature.

Package construction, die position, heating method and heat-dissipation paths can create measurable differences between dies.

For detailed reliability characterization, therefore, “test at 80°C” may not tell the whole story. Understanding the actual device temperature—and potentially the temperature differences within a multi-die package—can become part of interpreting the measurement results.

NanoCycler supports integrated heating for elevated-temperature testing, while external chambers or temperature-forcing equipment can be used when a wider environmental range is required.

Flexibility Without Sacrificing Execution Speed

Advanced characterization inevitably requires customization.

A fixed collection of predefined tests is useful for standard measurements, but research engineers frequently need to change algorithms, add device-specific commands or create entirely new experiments.

NanoCycler addresses this with a layered architecture.

At the higher level, Python-based recipes describe the test flow, device configuration, algorithms, parameters and data handling. Engineers can modify existing recipes or develop their own characterization procedures.

At the lower level, time-critical NAND sequences are executed directly by FPGA hardware.

This distinction is important. Using Python for test development does not mean executing high-speed NAND timing through Python. Python describes and controls the experiment, while the FPGA performs the deterministic high-speed operations.

The result combines two requirements that are often difficult to achieve simultaneously:

flexibility for R&D and high-speed execution for characterization and reliability testing.

From One Device to Parallel Reliability Testing

The same architecture can scale from a single test unit used for engineering experiments to systems containing many independently controlled NAND devices.

This becomes particularly important for reliability work.

A detailed characterization experiment may investigate one device, one block or even one wordline. A statistically meaningful reliability campaign, however, can require many devices running for days or weeks.

NanoCycler systems can therefore be configured with multiple Test Units and managed from a common environment. Large volumes of measurement data can be transferred to centralized storage for subsequent analysis.

The objective is to preserve the same low-level device access while moving from an individual experiment to parallel characterization and reliability evaluation.

The Real Test Starts After the NAND Is Connected

Modern NAND characterization is not about executing more read, program and erase commands.

It is about understanding what happens underneath them.

BER tells us how many bits are failing. Read-offset analysis helps us understand the available margin. Vth characterization shows how the cell-state distributions are evolving. Power profiling reveals the dynamic electrical behavior of the device. Sequence capture shows exactly what happened at the interface. Temperature profiling provides the environmental context in which all these mechanisms operate.

And because these measurements can be combined within programmable test flows, they can be correlated rather than investigated as isolated phenomena.

This is where device-level characterization becomes especially powerful: an engineer can investigate not only whether NAND fails, but how its behavior evolves toward failure and why.

For NAND technology development, controller development and reliability engineering, that is the information that ultimately matters.

Putting the NAND device into the socket is not the end of the test. It is where the real characterization begins.

This article is based on a technical article and customer demonstration originally reported by Michael Wang of Saniffer, NplusT’s partner in China. The original demonstration was performed using the NplusT NanoCycler NAND characterization platform.