Understanding resistive memory behavior through Set, Reset, Read operations and array-level analysis

Introduction

Resistive Random Access Memory (ReRAM or RRAM) is attracting significant interest for next-generation non-volatile memories and analog in-memory computing applications.

At the device level, its operating principle appears relatively simple: an electrical stimulus changes the resistance of a memory element, allowing information to be stored and subsequently retrieved.

However, developing reliable ReRAM technology involves much more than demonstrating resistance switching.

How consistently can individual cells be programmed? How accurately can their resistance be measured without disturbing the stored state? How uniform is the behavior across an array? Can intermediate resistance levels be programmed and maintained over time?

These questions become particularly important when moving from individual devices to memory arrays and, eventually, practical applications.

In a recent technical demonstration, NplusT presented the characterization of a 32 × 32 ReRAM mini-array using the TESTMESH platform, showing how programmable electrical measurements, array visualization, and flexible test algorithms can support device development.

Understanding the ReRAM Array

The device used in the demonstration was a 32 × 32 array containing 1,024 ReRAM cells.

Each cell consists of a resistive memory element and a selection transistor, forming a 1T1R (one-transistor, one-resistor) structure.

The selection transistor allows individual cells to be addressed while limiting unwanted interactions with unselected cells.

Three fundamental operations are required to characterize these devices:

• Set: Switching the cell toward a low-resistance state (LRS), corresponding to increased conductivity.
• Reset: Switching the cell toward a high-resistance state (HRS), corresponding to reduced conductivity.
• Read: Applying a sufficiently low voltage and measuring the resulting current to determine the resistance or conductivity of the cell.

Although these operations are conceptually straightforward, their practical implementation requires careful control of voltage amplitudes, pulse edges and durations, selection signals, measurement ranges, and timing.

The Read operation is particularly critical. An excessive read voltage may modify the resistance state, producing a phenomenon known as read disturb.

Accurate generation of low-voltage read pulses, combined with precise measurement of the resulting low currents, is therefore essential for reliable characterization.

Unlike conventional digital memory testing, which primarily evaluates logical states, ReRAM characterization requires precise analog measurements to understand the underlying device behavior.

From Individual Cells to Array-Level Characterization

One of the main objectives of the demonstration was to show how the behavior of an entire array can be measured and visualized.

The first operation consisted of reading all 1,024 cells under controlled electrical conditions.

For each selected cell, the system applied the required bias conditions and measured the resulting current within a defined acquisition window.

The results were then represented as a two-dimensional current map, with each position corresponding to a physical cell in the array.

This visualization provides an immediate overview of the conductivity distribution, highlighting differences between cells, abnormal regions, and possible systematic effects associated with particular rows or columns.

The demonstration then continued with Set and Reset operations, followed by additional array reads.

By comparing the resulting maps, engineers can identify which cells have changed their resistance state and which have remained substantially unchanged.

A particularly useful analysis is the differential current map, which displays the change in measured current between two operating conditions.

Rather than simply showing the absolute resistance distribution, this representation highlights the effectiveness of the programming operations across the array.

In the demonstrated device, some cells exhibited current changes of approximately 30–50 µA, while others showed limited switching behavior.

This was not a specially selected, ideal device. It was an early-stage engineering sample with significant nonuniformities and cells exhibiting abnormal behavior.

And this is precisely where characterization becomes valuable.

For researchers developing new memory technologies, identifying and understanding imperfections is more important than demonstrating ideal performance on a few selected cells.

Investigating Individual Cell Behavior

Array-level visualization is an efficient way to identify interesting or abnormal regions, but understanding the underlying electrical behavior requires more detailed measurements.

The demonstration therefore included current-voltage (I-V) characterization of individual cells.

By applying different voltages and measuring the corresponding current, engineers can investigate the conduction characteristics of the device and estimate its resistance.

For example, a measured current of 15 µA at 200 mV corresponds to an apparent resistance of approximately 13.3 kΩ.

For the particular device used in the demonstration, some cells exhibited low-resistance states around 4 kΩ and high-resistance states in the range of 120–200 kΩ.

These values are specific to the demonstrated technology and measurement conditions, rather than representative of ReRAM devices in general.

Combining array-level mapping with individual cell characterization creates a powerful methodology:

1. Identify abnormal or representative cells through array measurements.
2. Investigate their electrical characteristics using detailed I-V measurements.
3. Evaluate their response to different programming pulses.
4. Extend the investigation to cycling, retention, variability, and other reliability mechanisms.

This approach allows researchers to move efficiently between statistical analysis of the array and detailed investigation of individual devices.

Beyond Binary Storage: Multilevel Programming and Analog Computing

ReRAM technology is not limited to storing information in two resistance states.

By controlling the programming conditions, it may be possible to establish multiple intermediate conductivity levels, enabling multilevel storage or analog weight representation.

This capability is particularly interesting for analog in-memory computing, where the conductance of individual cells can represent the weights of a computational matrix.

When input voltages are applied to an array, the resulting currents can be used to implement analog vector-matrix multiplication, exploiting Ohm’s law and Kirchhoff’s current law.

However, exploiting this principle requires considerably more than the ability to switch between HRS and LRS.

The conductivity of each cell must be programmable with sufficient accuracy, and the resulting states must remain stable and distinguishable despite device variability, noise, drift, and aging.

Consider, for example, programming a cell to a target resistance of 50 kΩ.

A single programming pulse may not produce the desired value. Instead, engineers may need to develop iterative algorithms combining programming pulses and verification measurements.

Possible approaches include incremental step pulse programming, adaptive pulse amplitude or duration, and closed-loop Set/Read/Verify or Reset/Read/Verify sequences.

The appropriate strategy depends on the characteristics of the particular device.

For multilevel storage, it is also necessary to evaluate the distributions of the programmed resistance levels and their evolution over time and cycling.

The ability to distinguish four conductivity levels in a single measurement does not necessarily guarantee reliable two-bit storage.

The central challenge is not simply generating intermediate states, but controlling their accuracy, variability, and stability, considering drift, temperature and disturb effects.

These considerations are equally important for analog in-memory computing, where programming errors and conductance drift directly affect computational accuracy.

TESTMESH: A Flexible Platform for ReRAM Characterization

The demonstration was performed using an NplusT TESTMESH TMA-100 system equipped with a dedicated Extension Unit for the 32 × 32 ReRAM array.

The TMA-100 provides programmable electrical stimulus and measurement resources, while the Extension Unit adapts these resources to the electrical and connectivity requirements of the specific device. In this configuration, the Extension Unit implements the address-decoding functionality, connecting the TMA-100 resources to the selected and unselected bitlines and wordlines.

This modular architecture allows the main characterization platform to be reused across different devices and array structures, with application-specific hardware providing the necessary signal routing, cell selection, and measurement connections.

Such flexibility is particularly important for emerging memory technologies, where device architectures, terminal configurations, packaging, and electrical requirements can vary significantly between research projects.

From interactive measurements to programmable algorithms

An equally important aspect of the TESTMESH architecture is its software flexibility.

During the demonstration, basic operations such as Read, Set, and Reset were executed through an interactive interface.

However, these operations were not fixed functions embedded in a closed instrument.

The time-critical operations were implemented in C++ for performance reasons and made accessible through Python scripts, allowing users to define parameters and execution sequences

Engineers can therefore modify operating conditions, define new measurement sequences, and implement their own programming and characterization algorithms.

For example, a researcher can develop a test flow that:

• Programs a selected cell using a controlled pulse.
• Reads the resulting current and calculates the corresponding resistance.
• Compares the measured value with a target resistance.
• Adjusts the following programming pulse according to the result.
• Repeats the process until the desired programming tolerance is achieved.

The same programming environment can be extended to automated cycling, endurance characterization, disturb sensitivity analysis, multirange current measurements, and large-scale array analysis.

This is particularly valuable during technology development, when measurement methodologies and programming algorithms must evolve together with the devices being investigated.

From Measurements to Engineering Knowledge

The demonstration illustrated a practical characterization workflow, starting from basic electrical operations and progressing toward more advanced device analysis.

The combination of precise analog measurements, flexible stimulus generation, automated array addressing, data visualization, and programmable test sequences allows researchers to investigate questions that cannot be answered by simple functional testing.

Which cells respond correctly to programming? How does the resistance distribution change after Set and Reset? Which cells exhibit unusual electrical characteristics? How accurately can intermediate states be programmed? How do these characteristics evolve with cycling and time?

Answering these questions is essential for improving device technology, developing programming algorithms, and evaluating the feasibility of future memory and in-memory computing applications.

The most important lesson from the demonstration is that characterization is not about obtaining a perfect-looking measurement result. It is about transforming real device behavior, including its imperfections, into actionable engineering knowledge.

This is the objective behind the TESTMESH platform: providing researchers with the flexibility and measurement capabilities needed to understand emerging memory technologies and accelerate their development.

Acknowledgment

This article was adapted and expanded from a technical demonstration report originally prepared by Michael Wang of Saniffer, NplusT’s partner in China, and published on June 22, 2026. The demonstration was conducted by the NplusT team using the TESTMESH TMA-100 characterization platform.