NplusT has released NanoCycler HS20 for BGA132, BGA152, and BGA154 configurations, the fastest and most
feature-rich NAND characterization tester today, supporting 2.0 GT/sec NAND interface speed.
The company forecasts to come out with a further upgrade later this year, to reach 2.4GT/sec.
NplusT participated at the HiPEAC 2022 conference, held in Budapest, Hungary, June 20-22.
Tamás Kerekes presented the paper "POP-LEC Power Optimization of Low Energy Computing Devices before Prototyping", at the workshop "SMART4ALL - Capacity Building among European Stakeholders". POP-LEC is a running project funded by the SMART4ALL program FTTE 2nd Call, the technology transfer targeting an innovative product which helps IoT developers to accelerate their time to market. The partner company in this technology transfer is PCB Design, Hungary. The presentation can be viewed at this link.
The conference offered also the possibility to present a poster related to the previously executed HS-CHAR project, supported by the TETRAMAX program.
NplusT announces it has been granted a new patent entitled "Sistema per la caratterizzazione di memorie non volatili" ("Non-volatile Memories Characterization System").
The patented technology expands upon the company's intellectual property rights relating to non-volatile memory testing and characterization and has been successfully integrated into the NanoCycler test system.
Thanks to its proprietary architecture, NanoCycler proves to be the leading solution for the industry's most demanding NAND characterization needs, providing outstanding scalability (from single-socket development station until multiples of 84-socket racks), full, per-package independency for test execution and temperature control, cutting edge performance with data transfer up to 2.0GT/sec (2.4GT/sec coming soon) and an overall unmatched feature-rich hardware and software solution; to help SSD developers to increase lifetime and reliability of their products.
Low power consumption might be a mission-critical requirement in IoT applications. Early understanding of the power profile can accelerate time-to-market and reduce long and expensive iteration cycles. It is even more important considering that the power strongly depends not only on the electronic circuitry but on the device management algorithms as well.
POP-LEC (POwer Profiler for Low Energy Computing) aims at helping those developers who need to optimize their algorithms in order to reduce power consumption. It can be applied in the very early development stage, before the construction of the industrialized prototype. The POP-LEC environment provides a hardware and software platform where the algorithms to be validated can be executed, and integrates a high performance current profiling instrument.
“POP-LEC presents an exciting opportunity to enter a new market segment, merging our technology and knowledge of semiconductor testing with the technology transferred from our partner, PCB Design” - said Nicoletta Casini, CFO, coordinator of the POP-LEC project.
POP-LEC is being developed in the frame of the 2nd call of SMART4ALL FTTE (Focus Technology Transfer Experiment) with the collaboration of PCB Design.
The MOCCA 2021 has been assigned to the TenaFe NAND Characterization Team, lead by Curry Zhang & Sean Huang.
NplusT grants MOCCA (MOst Creative Customer Award) to users of NplusT products and services who leverage the most of the features and performance of such products making use of innovative approaches.
Tamas Kerekes, President and CEO of NplusT:
“I am really happy to see the level of understanding of the NAND, what Tenafe reached using NanoCycler. Curry with his team have developed a powerful infrastructure on top of the API provided with NanoCycler, and are using it efficiently to generate the necessary data and knowledge. This is the first time that MOCCA goes to China - I am extremely pleased about that, as I see a very fast evolution in technology and knowledge. The Chinese storage industry is evolving very fast, it is one of our strategic market targets: today we have several users of our products and technologies in China.
Curry Zhang, Senior Validation Manager of TenaFe:
“We've used NplusT NanoCycler for over 2 years, with the main purpose of NAND characterization, collecting data for our media management algorithm. As an SSD controller company, we need to adopt NAND from different vendors. Although we have our own controller and silicon, NanoCycler is still very helpful as a 3rd party tool. We use it frequently, every month, almost every week, for these reasons:
It gives us great pleasure to announce that NplusT has been featured in Startup Pill's 20 Best Italy Semiconductor Startups – Impacting The Electronics Industry.
The recognition is very appreciated and follows the 2021 ranking among the top 10 semiconductor companies in Italy.
NplusT hosted a webinar titles "Why is Your SSD Not Working?" on the complexity and issues of NAND characterization.
The webinar was held on March 19, 2022 and was attended by over 250 industry experts.
The full recording is available at this link.
NplusT released the latest member of the NanoCycler family, the HS20 BGA152. This tester is the first on the market reaching the 2,000 MT/sec data exchange rate between tester and NAND devices.
“SSD performance is increasing tremendously and NAND vendors are keeping pace. SSD makers need to characterize the NAND in conditions as much similar as possible like the NAND will work in the final application, including interface speed. Reaching the 2.0GT/sec transfer rate is an important milestone of our roadmap, ensuring our customers to apply solid, proven solutions in the right time. We are continuing our development and we plan to release further enhancements reflecting the ONFI 5 standard like the BGA154 package support, the new LP-NVDDR4 protocol and also reaching 2.4 GT/sec and beyond” - said Tamas Kerekes, President and CEO of NplusT.
NplusT took part in the workshop titled "Finding the way of solving reliability issues of the next generation NAND flash memories", organized by CCF YOCSEF Shanghai (China Computer Federation, Young Computer Scientists Engineers Forum) and held the December 18, 2021.
The meeting was a great occasion to exchange experience and ideas by several industry and academic experts.
Tamas Kerekes presented the paper "NAND Characterization for ONFI5 and Beyond". The integral version is available at this link.
NplusT delivered 3 large size NanoCycler HS equipment to an important Chinese customer.
Based on its innovative architecture, the system allows to execute up to 252 fully independent tests, including package level thermal control, on NAND memories at the same time. The communication speed with the devices under test reaches 1.6 GT/sec on two channels in parallel, with zero-overhead pattern generation and pattern matching.
These equipments - being able to test the latest and future generation of NAND devices - aim at enhancing the customer’s development flow in the implementation of data centers and high-performance storage applications.
Tamas Kerekes, President and CEO of NplusT declared: “When building the equipment, we had to face the serious challenge of the component shortage. Our engineering team provided an excellent answer: the necessary design changes further improved system performance. We have been able to design, qualify, manufacture and test in a really short time. Now, our expectation is to see our customer executing efficiently their characterization and sorting tasks, we will provide them all necessary support. The delivery of these equipment also represents an important milestone to increase our presence in China, which is our fastest growing market today.”
NplusT is pleased to announce that the version 6.0 of the NanoCycler Function Library has been released.
The upgrade is a huge step forward for the productivity of the user community in developing characterization programs. The main features are the following:
The library comes with an exhaustive documentation. For further details, please contact the NplusT support team.
It gives us great pleasure to announce that BestStartup.EU has ranked NplusT in the top 10 semiconductor companies in Italy (see 10 Top Semiconductor Startups and Companies in Italy).
Our customers’ needs drive our continued investment in R&D and updates to our product portfolio. This way we can offer the best time-to-market at reasonable cost and effort. We see this appreciation as a further validation of our roadmap.
In response to the ever increasing number of cyber-attacks and in order to ensure the same level of safety in all working locations (main office, lab and home offices), in March 2021 NplusT has completed a series of improvements aimed at further raising the company’s IT safety standards.
The improvements include Cloud Managed Security & Total Security, featuring the latest technologies, as well as Company’s internal guidelines, updated in the management of virtual and physical development machines.
Please feel free to contact us should you have any questions regarding NplusT’s IT safety policy.
Progetto realizzato con il contributo europeo Regione Umbria POR FESR 2014-2020
Asse III Azione 3.7.1. –
Avviso Bridge to Digital 2020.
Project implemented with funds from the European Union and Umbria region under the POR FESR 2014-2020 Axis III Action 3.7.1. – Bridge to Digital 2020 Public Notice.
Every year, NplusT assigns the MOCCA (MOst Creative Customer Award) to those users, whose innovative applications and solutions enhance the utilization and performance of NplusT products. The year 2020 MOCCA has been assigned to Niccolò Castellani, R&D Engineer at CEA-LETI, Grenoble, for developing a software platform for the automation of non-volatile memory test flow execution on NplusT’s test equipment.
Tamas Kerekes, President and CEO of NplusT:
"I am really happy to see the way how Niccolò and the LETI team approached their specific requirements. The software framework, which Niccolò has created on top of the execution environment of the tester, enables the easy development of characterization programs for a wide range of novel, emerging non-volatile memory technologies. We plan to continue supporting LETI, providing innovative test platforms which enable fast and accurate measurements, contributing to develop high-performance, low-power, reliable storage devices."
Niccolo Castellani, R&D engineer at CEA-Leti:
"I started this project a couple of years ago, having already experienced test developing and data analysis for research and industrial requirements. I’ve been always convinced about the real need of versatility for the R&D of merging memories testing. Only NplusT was able to provide the right tools and the right support team to accomplish my objective: a hardware to user interface getting plug-and-play new designs and new algorithms in its environment. I’m willing to continue this great collaboration."
The speed and complexity of the latest TLC and QLC flash technologies set new challenges in designing large capacity high performance SSD devices, from the hardware (signal integrity, power management) and the firmware (flash algorithms, error correction) point of view. Massive amounts of accurate data must be collected and analyzed to characterize the flash endurance, errors, defects, operation’s timing and power.
NanoCycler HS, bundled with BarnieMAT data analytics, provides the best-in-class and most cost effective solution for the exploration of the NAND memories.
Supports endurance and functional testing of NAND devices by providing C++ and Python API with full ONFI command set and with customizable signal sequences.
Exercises and stresses at-speed - up to 1.6 GT/sec – the devices under test faithfully replicating the use conditions of the application.
Provides high-accuracy - 10 mV precision - programmable power supplies for accurate voltage margins analysis.
Captures the power consumption for each supply at 50 nsec sampling rate with 1 mA resolution. Flash operations power consumption data are processed in real time to provide high resolution current consumption traces, and key metrics (peak, average, distributions) over long period of time.
Characterizes the flash interface timing with 1 nsec I/O edge placement and 20 nsec flash response time acquisition.
Has a scalable and expandable architecture, from 1 to 48 test sites, to optimize cost and long term investment.
Allows full independence of the test sites where each device under test can run at individual temperature, timing, voltage levels, with different test programs.
Integrates the data analysis environment to post-process and present the results to accelerate time to product.
Highest quality characterization results at the lowest cost and effort – NanoCycler HS represents a future-safe investment to design high-performance reliable mass storage devices.
Building on their successful memory testing technology, NplusT has extended this expertise to the design, validation and characterization of image sensor devices.
The array-organized analog cell structure of the image sensor is similar to non-volatile memory and lends itself to the reuse of the core NplusT memory testing technology that has been production-proven for decades.
Specific needs of data analysis to support image sensors has resulted in additional innovation with the extension of BarnieMAT, NplusT’s popular array data analysis tool, adding an additional library containing processing functions dedicated to image sensors.
NplusT announces version 7 of the BarnieMAT array analysis software, building on the success of the previous versions and including the following major extensions:
BarnieMAT has been widely recognized for its intuitive user interface and insightful analysis & presentation of array data for product development and device characterization. Version 7 also includes:
NplusT has been granted funding from the European Commission in the framework of INNOWWIDE call-2 for the "Innovative Test Equipment for Mass Storage Devices" project, in short "ITEMS", ranking 26th among 70 grantees and over 600 candidates.
INNOWWIDE, a Viability assessment of collaborative and INNOvative business solutions in WorldWIDE markets, is a Horizon 2020 project that will fund European innovative SMEs and start-ups to conduct Viability Assessment Projects (VAPs) in markets outside of Europe.
The aim of the project is the technical and market validation of a product concept. This product – ITEMS – is a high performance test equipment based on an innovative architecture which allows to provide world class performance at affordable costs. The core technology has been already developed and applied in other products of NplusT and the related patent is pending.
ITEMS will help electronics manufacturers to build products matching the requirements of rocketing storage needs, increasing calculus and processing power in applications like machine learning, artificial intelligence, autonomous drive. The primary target market is China but the product offering will be extended to Taiwan, Korea and other developing countries in the South-East Asia region.
NplusT has implemented all the measures provided for in the Italian legislation in force and all the measures promoted internally regarding the COVID-19 emergency.
All the company's activities are guaranteed consistently with our business continuity plan and in full compliance with the measures adopted in order to ensure the prevention and the safety of the personnel.
For all your needs, you can rely on our Customer Care which can be reached via e-mail at firstname.lastname@example.org.
NplusT took part in the TETRAMAX poster session held at the 2020 edition of HiPEAC, the main European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems, attracting over 500 delegates each year.
The poster session showcased the projects funded in the framework of the European "Smart Anything Everywhere (SAE)" initiative, in the domain of customized low energy computing (CLEC) for CPS and the IoT, including the "HS-CHAR: High Speed Characterization of Mass Storage Devices" technology transfer project carried out by NplusT and PCB Design and devilered in December 2019.
The results of the "HSCHAR" project contributed to upgrade NplusT's technology for NAND characterization, paving the way for the forthcoming release of NanoCycler High Speed, the best-in-class and most cost effective solution for the exploration of the NAND memories.
The MOCCA 2019 (MOst Creative Customer Award) was assigned to Nellina Mautone, appreciating her activities in flash data analysis using BarnieMAT.
Tamás Kerekes, President and CEO of NplusT:
“We are really appreciating the cooperation with Nellina and with the entire Infineon team.
The developed toolset, based on our BarnieMAT technology, is an excellent example of efficient management of large quantities of data aimed at extracting and presenting information in a way that is intelligible to the human brain, in order to reach faster and safer decisions. Infineon is also an important partner in the definition of the product roadmap, asking for new features according to the changing needs of the user community.”
Nellina Mautone, Staff Engineer of Infineon Technologies:
“When we started our project around a year ago, one of our main challenges was the application of BarnieMAT, until then used for technology analysis, in a different environment for processing manufacturing data. Our team, which involves several students and benefits from the expertise of Mr. Rudolf Ullmann (Lead Principal Engineer of Infineon Technologies Munich), needed and continues to need more features and better performance.
The integration with an external Python-based data processing environment is an answer to ever-challenging demands, and proved to be an enabler of our work. We see BarnieMAT as a well-structured and well-supported tool, matching our requirements and ensuring the maturity which allows us to focus on our analysis tasks.”
The webinar "NAND Characterization: Why and How" is now available in the website's Demo section.
The video provides a thorough insight on how understanding the NAND is central to the memory manufacturing process, and how NanoCycler can help manufacturers tackle and solve reliability and performance issues. The webinar is available at this link.
NplusT is participating in the 2nd open call for Value Chain Oriented and Interdisciplinary Technology Transfer Experiments in the framework of TETRAMAX, the #1 innovation hub for digitizing European industries in the domain of customized and low-energy computing (CLEC).
Tamas Kerekes presented the technology transfer project "HS-CHAR: High Speed Characterization of Mass Storage Devices", which is being developed together with PCB Design, during the annual TETRAMAX Partners Meeting, held in Aachen on September 26.
TETRAMAX is proving to be a very efficient vehicle to promote small size projects, as Tamas said:
"Let me share you about my experience and consideration about the TETRAMAX projects and in particular about the call related to the bilateral technology transfer.
My company is a small SME working in the semiconductor/electronics industry. We spend more than half of our engineering resources on R&D. Even so, we cannot develop all technology we need by ourselves and we need to access technology of others. Contributions of national and EU funding are extremely useful to support our business growth. There are many calls and opportunities. On the other hand, we don’t have all resources to monitor and select the calls, even less to write many applications (a typical Sunday night task). So we need to focus on the opportunities where either: 1) the success rate is very good and the funded amount is high or: 2) the preparation of the application requires a reasonable amount of work. In both cases, the fast turnaround time (from application to final reporting and cashing) has to be short.
From this point of view, I consider TETRAMAX our best experience:
We have been advised about the opportunity by a TETRAMAX partner, without the need to monitor and study.
The preparation of the application is easy - of course once we have the content. We need to provide only the important data in a condensed way. I think this is a winning approach from the evaluation side as well.
The contracting procedure is easy again.
I warmly suggest TETRAMAX to other SMEs and I hope it will be a long success story!"
NplusT and JWILL have taken part to the 2019 edition of SEDEX, in Seoul. The show is one of the biggest events for the semiconductor industry worldwide, covering the fullspectrum of the memory supply chain and showcasing the latest advancements to more than 13000 visitors over three days.
"SEDEX has been a great opportunity to introduce our NAND characterization and memory test solutions to South Korea's industry professionals" states Tamás Kerekes, President and CEO of NplusT. "The country is one of the main global innovation hubs and a strategic market for our products. We look forward to strengthening our partnership with JWILL and provide our technology to Korea's key industry players and research centers."
“The global network of NplusT has been recently expanded by signing a cooperation agreement with APMD Solutions. Our goal is to boost sales and customer support in the US market. The fast growing need for storage devices, driven by industrial, automotive and AI applications, offer an exceptional opportunity for our NAND characterization and testing technology” declares NplusT’s President and CEO Tamas Kerekes.
“APMD Solutions’ huge domain-specific experience is the right basis to increase our presence in America. We look forward to cooperating with APMD to bring additional support for our US Customers”.
NplusT has taken part in the 2019 edition of Flash Memory Summit in Santa Clara, California, the leading event for non-volatile memory and storage.
NplusT introduced the new version of NanoCycler which supports NAND characterization at 800 MT/sec and presented additional products and services helping SSD and other storage device makers obtain fast time-to-market.
Tamas Kerekes, President and CEO of NplusT, also tackled the reasons why NAND characterization at high speed is essential to building efficient and reliable SSD devices during his speech "Characterizing NAND Devices at High Speed - Why and How?".
The presentation is available for download via this link.
NAND characterization is essential to understand features and behaviors of the latest components. It enables you to fine-tune the device management algorithms and the error correction strategy, to obtain the target performance and reliability of your SSD or other storage system.
Our NanoCycler - especially developed for NAND characterization, embedding dozens of years of experience and supported by a team of experts - provides a cost-effective, easy-to-use, flexible environment, matching the characterization requirements of the latest generation of NAND devices (3D, QLC, 1.2GT/sec) and it is extendible for other emerging technologies like X3D, MRAM, …
Come to visit us at Booth # 801
Schedule a meeting and demo with us.
The new version of NanoCycler, beyond pushing up the highest transfer speed to 800 MT/sec, provides additional features like Vpp management and thermal protection. First units are shipped from July 2019. The new tester unit is fully software compatible with the previous release.
The MOCCA 2018 (“MOst Creative Customer Award”) has been assigned to the GAMAX team, appreciating more than ten years of intense cooperation in the software development arena. GAMAX provides a continuous support – based on outstanding knowledge and on innovative technology – and many of NplusT products embed GAMAX code. From 2018, GAMAX is also using NplusT array data analysis software tools which, integrated with MATLAB, opens the gate to new applications on regular structures.
Tamás Kerekes, President and CEO of NplusT:“GAMAX is the ideal partner in co-development of our software. Their quality and reaction time when support is needed is excellent. I am particularly pleased about GAMAX innovative attitude and the way they introduce new technologies without raising the risk factor. Last year we worked with GAMAX also in the opposite way, transferring our array data analysis technology to them and I can say this was the fastest and most efficient introduction of the toolset since we market it.”
Géza Homonnay, Managing Director of GAMAX: “We are proud to receive this MOCCA award from one of our most important partners, showing our ability to fulfill interesting challenges. We have been active in software development and other software related activities during the last 30 years. Having received similar acknowledgement from Microsoft for software localization, from Oracle for software consulting and from MathWorks for software distribution, we will be strengthening our efforts to serve our valued partners the best possible way.”
NplusT signed a business development agreement with JWILL Technology. JWILL is going to distribute NplusT products and services in Korea. This collaboration is meant to help NplusT to extend its market and supply leading edge memory test and characterization solutions to Korean memory and storage device maker companies.
The article “Getting Meaningful Data from NAND Characterization”, written by Tamás Kerekes and published in the online newsletter SSDFans in China, provides useful hints regarding the correct implementation and execution of NAND characterization. Download the English translation here.
NplusT and GAMAX Laboratory Solutions started a cooperation to develop new data analysis possibilities by combining the dedicated array processing features of BarnieMAT with the general high volume data analysis possibilities of MATLAB. As the first step, a training was given to the GAMAX engineering team.
The training focused on the advanced utilization of the BarnieMAT software and on the array data generation using a NanoCycler tester.
Tamas Kerekes, President and CEO of NplusT and Tibor Turkevi-Nagy, Managing Director of GAMAX Laboratory Solutions, expect a market-ready product for the second quarter of 2019 which will be marketed by both parties for the specific application areas.
The 2018 Flash Memory Summit is approaching quickly: NplusT will be there demonstrating the latest hardware and software solutions to fast track your memory technology. Our engineering test platforms and our data analysis software tools – developed especially for the NVM world and embedding the knowledge and experience of a long learning path – helped our customers to successfully bring up and consolidate emerging technologies very fast. We support our partners in the technology and product development as well as in the high volume production ramp up and monitoring. We have been busy over the last decade and we have expanded to become a worldwide vendor for companies – such as IDMs, foundries, technology providers, research institutes in Europe, in America and in Asia - which successfully applied the RIFLE tester and/or the BarnieMAT array analysis software.
Visit us at Booth 809 to try the tools we can provide to give you additional insight into your
memory technology !
We would be pleased to show you our offerings:
The recently released 5.2 version of BarnieMAT provides significant improvements as:
NplusT continues to invest in the toolset providing periodic enhancements for an always larger customer base.
interventi di cui al POR FESR 2014-2020 Asse I - Azione 1.1.1. “Sostegno ai progetti di ricerca industriale e sviluppo sperimentale” - Titolo Progetto «NPTE (New Parallel Test Equipment: nuova piattaforma di testing applicata dalle industrie di semiconduttori nella fase di sviluppo di nuove tecnologie e di nuovi dispositivi a semiconduttore»
Il progetto di ricerca e sviluppo sperimentale consiste nella realizzazione di un prototipo funzionante di piattaforma di testing concepita per l’industria semiconduttori. NPTE trova applicazione nella fase di sviluppo di nuove tecnologie e nuovi dispositivi a semiconduttore, in particolare per le memorie integrate in ‘System-on-Chip’.
The year 2017 MOCCA (MOst Creative Customer Award) went to the MICROSEMI team for their cooperation in the development of the GARDA test solution.
GARDA has been created for understanding functionalities, performances and reliability of next generation memory devices targeting mass storage applications. For achieving the required 1.6GT/s transfer rate between the memory tester and the device under test, a dedicated hardware solution has been developed. The software architecture and environment have been transferred from the RIFLE platform, extending it with dedicated FPGA front end code.
“I prefer to work with teams like Microsemi” - Tamas Kerekes, President and CEO of NplusT says. “This team is very demanding, they know what they want to obtain and they are willing to cooperate in the identification and implementation of the optimal technical solutions. The 14-week delivery time would have been impossible without such a cooperation”.
“The Storage industry is continuously looking for new non-volatile memory technologies and being able to technically vet each of the new options is key for deciding where to invest the R&D dollars. NplusT offers a unique combination of hardware and software capabilities for memory testing. The collaboration between the 2 teams has been amazing and it is worth highlighting that the platform Garda was delivered on time meeting all the required technical specifications”, said Rino Micheloni, Technical Fellow in the Performance Storage business unit and Managing Director of Microsemi Storage Solutions Italy. “We are looking forward to expanding this collaboration in the near future even further”.
The version 5 of BarnieMAT has been released for beta testing. Beyond a bunch of functional and usability upgrades, the v5 allows the scripting in Python language. If you want to be part of the beta testing group, please contact Tamas Kerekes email@example.com.
The NplusT engineering team, in cooperation with FPGArt, implemented and tested with success a new technology, pushing up the communication speed between the tester and the device under test. The experimental solution, applied for a next generation NVM device, reaches 1.6GT/sec data transfer rate. Mastering this new technology, the application range of the RIFLE test system extends and covers the latest mass storage components, stil maintaining the cost advantage and faster time-to-result related to competitive solutions.
NplusT released a new non-volatile memory cycler equipment, powered by the well-established RIFLE-M core. An add-on module extends the tester resources for the parallel management of multiple devices. Specific micro-chambers are installed to individual thermal control of the devices under test. With this new product, cycling operations can be performed maintaining features and performance of RIFLE-M, without the compromises due to large size cycling boards. Benchmarking data evidences that the cycling times are drastically reduced related to the commonly used architectures (device and equipment dependent).
NplusT Team has been recently interviewed by the regional TV troupe!
Enjoy the broadcasted clip.
The yearly MOCCA (MOst Creative Customer Award), recognising the user with the highest contribution in the application of NplusT tools, was assigned to the STMicroelectronics Team lead by Luisa Fracassini and composed of Domenico Ausilio, Andrea Boroni, Emanuele Capitanio and Sergio Pozzi from QMS, CSR & Central Labs department.
As a result of development and evolution of the software tool SIREN, built on NplusT LabVisor technology, hundreds of equipment and instrumentation installed in several Qualification and Validation laboratories are being taken under control. SIREN today serves a large community of users in their daily tasks such as monitoring, booking, maintenance and utilization statistics.
Since we started the project, I was always impressed by the strong focus of the team to create a tool which is really useable and used. Continuous new ideas of improvement and extension - together with active cooperation in the development - helped to obtain the status that today SIREN is one of the software tools created by NplusT which is the most extensively used.Tamas Kerekes, President and CEO of NplusT
SIREN has been conceived since the beginning as a growing tool with the ambitious purpose to arrive finally to manage with a single system multiple and heterogeneous Electrical Qualification and Validation laboratories. This long term vision target could be achievable only with a deep, side by side interaction and cooperation between various ST entities and NplusT, working on the development of one step in an optic of compatibility with the future ones.Luisa Fracassini, QMS, CSR & Central Labs Manager, STMicroelectronics
Commented a Test Engineer during a BarnieMAT training. We are willing to integrate customer needs into our tools so we are considering this new feature in the evolution roadmap.
The already rich set of functions of RIFLE-M has been extended by the possibility of measuring access times of memory arrays at high accuracy. This new function, implemented as a dedicated FPGA module, generates programmable signal skew with a 1 nsec resolution. The feature is supported by an application specific calibration software in order to compensate the overall system skew including test board. In the same time, shmoo functionality covers the access time as well. One of the key customers of RIFLE-M declared that the availability of this new function allows the execution of the entire design validation flow on RIFLE-M so other test platforms can be “switched off”.
The version 4.3.1 of BarnieMAT has been tested under Windows 10, extending the compatible platforms of Windows 7 and Windows 8.
Sidense Corp., a leading developer of silicon-proven, embedded Non-Volatile Memory (NVM), has deployed our BarnieMAT software as their internal array data analysis platform. After the startup and training session in Ottawa, Brent Taylor, Sidense’s Director of Product and Test Engineering, said:
Our test team is eager to start using BarnieMAT as a way to accelerate the evaluation cycle time for our 1T-OTP memory. We look forward to an excellent return on our investment in this tool.
The MOCCA (MOst Creative Customer Award) 2015 has been assigned to the NVM R&D team of TowerJazz, Israel. Every year NplusT assigns MOCCA to the customer team which applies NplusT tools in the most innovative and productive way. The team, led by Mr. Micha Gutman NVM R&D Mgr. and composed of Mr. Vladislav Dayan Expert Design Eng., Mr. Tamir Eshkoli Senior Staff Rel Eng., Mr. Dmitry Lechinsky Test Eng., Mr. Daniel Nahmad Staff Device Eng. and Mr. Eran Yeroslavich Test Eng., replaced a traditional ATE with RIFLE and BarnieMAT in the design validation and characterization of new non-volatile memory technologies.
I was impressed how fast the TowerJazz team started to work efficiently with our tools and, which is most important, to obtain the expected results. We highlight the ‘time-to-result’ as one of the most important added value of our toolset and this project is a perfect demonstration of it.Tamas Kerekes, President and CEO of NplusT
Our decision of using RIFLE and BarnieMAT in our design validation process outperformed the expectations. I was surprised by the progress of validation of every single device function, as the result of a strict collaboration of NplusT and our team. The easy and flexible programming, together with a good visibility on the device status creates an important step forward in our workflowMr. Micha Gutman, NVM R&D Mgr. TowerJazz, Israel